1. Field of the Invention
This invention relates to the field of electronic circuit design and, more particularly, to designing circuits using high level programming languages.
2. Description of the Related Art
Traditionally, designs for electronic circuits have been specified using a hardware description language (HDL) such as Verilog or VHDL. HDLs allow circuit designers to design and document electronic systems at various levels of abstraction. Designs for programmable logic devices (PLDs), such as field programmable gate arrays (FPGAs) and application specific integrated circuits (ASICs), can be modeled using an HDL. The design then can be simulated and tested using appropriate software-based design and/or synthesis tools.
One recent trend in circuit design has been to use high level programming languages (HLLs) to design electronic circuits. For example, a circuit design can be specified initially as a program written in an HLL such as Fortran, C/C++, JAVA, or the like. This approach allows a developer to concentrate on an algorithmic solution to a problem rather than the specific hardware involved. A variety of different tools are available which effectively translate the HLL program into a synthesizable netlist or other software-based circuit representation.
Typically, the process of generating a circuit design from an HLL program involves inferring gates directly from the HLL program. More particularly, a compiler builds an internal representation of the HLL program in the form of a control data-flow graph. From that graph, register transfer level (RTL) descriptions and netlists can be generated. The results further can be processed using conventional HDL development tools.
Despite the advantages of HLL-based circuit design, disadvantages do exist. One such disadvantage is that conventional HLL-based circuit design typically requires a significant amount of processing resources to understand the HLL program at compile time. One reason for this is that conditional instructions, such as “if” instructions, must be analyzed and resolved. If one branch of the conditional instruction is longer than the other, additional stages of circuitry must be inserted into the shorter branch so that the two branches essentially require the same amount of time to execute.
Another disadvantage is that the structure of the original HLL program is lost when the hardware representation is generated. A direct conversion of the HLL program to gates is performed without any intermediate output. In consequence, any debugging that may be necessary must be performed at the RTL level, rather than on the HLL program. Debugging at the RTL level, however, does not provide developers with an intuitive means for correcting errors or bugs.
It would be beneficial to provide a technique for designing a circuit using an HLL that is more intuitive than existing technologies and which overcomes the deficiencies described above.